A phase locked loop (PLL) is a well known circuit for generating signals having a predetermined frequency relationship with a reference signal. In its most basic form, a PLL comprises an oscillator that is controlled by means of a feedback loop. The feedback loop takes the output of the oscillator, compares it to the reference signal and adjusts the oscillator accordingly. The PLL may comprise a phase comparator for comparing the phase of the output signal with that of the reference signal, and a control means, such as a charge pump, for outputting a signal which either increases or decreases the frequency of the oscillator in dependence on the comparison. A low-pass filter can be used to suppress spurious noise created by the control means before it reaches the oscillator.
The feedback loop may also comprise a divider for dividing the output signal before it reaches the phase comparator, and in this way the PLL can be controlled to generate signals having frequencies which are integer multiples of the reference signal frequency. Some PLLs are able to generate output signals which are non-integer multiples of the reference signal frequency by applying a non-integer divider in the feedback loop. For example, a sigma-delta circuit can be used in the feedback loop to apply varying integers which nonetheless average to the required fraction. One example of a frequency locked loop (FLL) according to this type is shown in US patent publication no 2009/0033376.
However, the divider in such PLLs (whether integer or fractional) tends to be power hungry, and therefore they are not suitable for all applications. An alternative method of generating signals is required.